June 16, 2018

Integrated Motor Controllers V2: Searching for the noise

Remember how I said I was going to re-do the integrated motor controller using the new TI DRV8323 chip?  Well, I did that.  First round of boards came in and had a few errors, but I think I've found them all. 

Changes:

  • DRV8323RS for gate drive, buck converter, and current shunt amplifiers
  • Smaller footprint - 37x37mm
  • Reasonable shape!  Square mounting hole pattern, centered position sensor
  • All components (except for the position sensor) on the top side - the underside is flat for easy mounting and heat-sinking
  • Designed for through-board cooling, with FET pads thermal-via'd to the underside
  • True 4-layer design, 0402 package passives wherever possible, 6 mil trace/spacing, to make it small
  • Smaller buck passive, smaller CAN transceiver

Front:



Back side.  Notice how empty it is.


Attached to a motor.  Unfortunately I forgot to take a picture of the board before doing a lot of reworking on it, so it's kind of ugly now:


After correcting a couple easy-to-fix mistakes with bodge wires (forgot to connect the CAN transceiver standby pin to ground, routed one of the wrong current sense amplifier outputs to the A/D, since I'm only using 2 out of the 3), the controller worked (as in, it was able to spin a motor), but it was clear immediately that something was wrong with the current sensing.  There was tons of audible noise once the current loop was closed, so I took a look at the measured phase currents.  Here's a plot of the output from the 2 A/Ds, while setting a constant d-axis voltage and slowly rotating the motor by hand:


The first current measurement looks beautiful, but the second one is absolute garbage.  The big spikes are ~750 A/D counts, which would correspond to 15 amps.  Time to break out the scope:

Here's the output of the amplifier:  The big spikes are at around 8.7 kHz, but there's also a lot of higher-frequency noise:


Zooming in:  There are also smaller pulses at 675 kHz.  That's almost certainly the switching frequency of the buck converter on the DRV chip:


Next step was to see if this noise actually showed up on the input to the amplifier, or whether it was showing up after the amplifier or inside the chip somehow.

Test points attached:


I measured in a few places.  First, directly across the shunt.  As expected the noise didn't show up directly across the shunt - unless there were actually many amps of noise flowing through the 1 milli-ohm resistor, there shouldn't be any volts across it.  

I moved the test points ot the two vias directly before the input to the DRV:


And the noise appeared.  For these measurements, the Rigol didn't really have the resolution, so I broke out the Yokagawa DL708E, which has 8 isolated channels with 12-bits of resolution (4 bits more than the Rigol).


After two evenings of probing around and making very little progress, I finally found the two layout errors that combined to cause this problem.

Here's the board with ground highlighted.  The logic ground up top is on an inner layer, and the power ground below is on both the bottom plus an inner layer.  Take a look at the border between the two:


The three highlighted traces crossing the border are the traces for sensing across the current shunts (and from the sources of the un-shunted FET).  Yep, I accidentally forgot to connect the logic ground to the power ground.

Which brings up the question:  How did the board even turn on at all?  The traces from the shunts are inputs to amplifiers, and should be high impedance.  It shouldn't be possible to power all the logic through them.  And why didn't Eagle yell at me when I ran DRC, or show any air wires?

Taking a closer look at the noisy shunt, this time with the inner layers visible:


Oh.  Oops.  When I dropped in the vias for the shunt, the ones on the ground-side of the shunt got automatically connected to the internal ground plane.  Which is also why the logic ground plane didn't show up as being disconnected from the power ground plane in the DRC.  So all the power for all the logic was passing from the power ground, through the current sensing trace, through the vias, to the logic ground.  That'll do it.  

At least I've learned a good lesson from this:  Always add kelvin connections to the shunt footprint in Eagle, even if the actual shunt resistor doesn't have them.   This way, the current sensing traces won't be part of the ground net, and this kind of mistake would be impossible.

New boards are on the way, so hopefully I'll be able to do some stress-testing in the next few weeks.  On the firmware side, I plan on finishing all my autocalibration stuff soon.  Then I'll easily be able to slap this controller on all my small motors, and collect a huge pile of motor data.

5 comments:

  1. I wonder how you decide on the values for bypass caps? It seems you dropped the electrolytics on the the bottom, any reasons behind that?

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    1. Ah, you mean all the capacitance on the DC link, right by the transistors? That's an excellent question I don't yet have a 100% satisfactory answer for. For the gigatroller (http://build-its-inprogress.blogspot.com/2016/08/introducing-gigatroller.html) I ran it at 200A with only 66 uF of film caps on the bus, and that worked out just fine.

      I've been doing some SPICE modeling of it recently, to get a better understanding for how the source impedance, load, and dc link capacitors affect current ripple form the source current ripple in the capacitors, and voltage ripple across the capacitors. I'll probably do a post on that when I have a better answer.

      So far, current ripple in the capacitors seems like the most important factor, and electrolytics have pretty garbage ripple current ratings. Anecdotally, that's often the part of hobby ESCs that fail - they usually have almost no ceramic capacitors on the bus, but some giant electrolytics, which desolder themselves or have their leads fail under heavy load.

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  3. Looks like a solid upgrade; love the minimized footprint. I like the reasoning behind the through-board mosfet cooling with vias, but do you think the thermal dissipation on the backside will be sufficient? Would putting them on the backside benefit from airflow generated by the motor can, or is clearance the main concern?

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    Replies
    1. Detailed thermal testing post coming up shortly.

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